The present invention relates to a voltage limiter for very low consumption and ultra high speed logic circuits, the voltage limitation considered concerning the voltage deviation between the low and high levels, or logic 0 and 1.
The voltage limiting circuit of the invention relates more particularly to directly coupled field effect transistor logic circuits, called DCFL or "Direct Coupled FET Logic", formed with normally off transistors, whose threshold voltage is positive. The voltage limiting circuit is formed by a field effect transistor, of normally off type, whose gate is connected to the drain, and which is fed through a resistor connected to the drain.
DCFL logic circuits perform better with an increase in the load current through the resistor which feeds the transistor, but in this case the resistance of the transistor in the enabled condition increases. In order to ensure correct operation of the logic circuit it is preferable to choose a smaller load current and to compensate for the loss of speed which results therefrom by a reduction of the switching time of the logic circuit by reducing the voltage deviation between the low and high logic levels.
Such limitation of the voltage deviation is obtained by a single field effect transistor, fed by its drain through a load resistor and whose gate is connected to the drain, this transistor and its load resistor being of the same type and of the same characteristics as the transistors and their load forming the controlled logic circuit.